1. Field of the Invention
The invention relates to a data buffer memory of the "first-in, first-out" type, having logic means for ensuring that an input for data to be written is situated as near as possible to an output for data to be read, depending on the filling of the buffer, thus forming an uninterrupted content of the buffer, furthermore having an input bus for transporting data to the buffer, notably to an input of a register thereof assigned for this purpose, and an output bus via which data are read from the buffer, notably from a register assigned for this purpose.
2. Description of the Prior Art
A variety of data buffer memories of the described "first-in, first-out" type are known to serve as buffer devices in digital data processing and communication systems at locations where differences occur in the rate in which input data is supplied and the rate in which output data is consumed. A number of the known buffers are characterized by simplicity of construction, notably by a substantially repetitive nature of the various sections of the buffer. An example in this respect is formed by the buffer described in U.S. Pat. No. 3,745,535. A problem with buffers of this kind is that, if the capacity of the buffer is n sections, a message which is applied to an empty buffer appears on the output thereof only after n clock pulse cycles. Particularly if n is large (for example, 32) this may give rise to unacceptable delays in practice. These buffers are thus characterized by a so-called fixed input and a fixed output.
As has been mentioned above, the buffer in accordance with the present invention is of the so-called variable input/variable output type, based on the fact that use is made of an input bus and an output bus. Buffer memories of this kind, comprising a variable input and a variable output, are also known from British Pat. No. 1,497,774. Therein, a variable input location and a variable output location of the buffer can be activated by means of counting devices and decoding selection networks coupled thereto. The advantage of such an arrangement comprising a variable input and a variable output is that the data need not be transported in order to reach the output. Particularly in cases where the buffer is empty or almost empty, delays are thus prevented. However, a major problem of the latter buffer devices is that the complexity of control increases as the number of sections of a buffer is larger. Counters having a high counting capacity and complex decoding selection networks for the inputs and outputs to be assigned, or other additional steps are then required. Moreover, the linking of a number of small buffers in order to form one large buffer is not possible without additional complications.